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4.2.5. LVDS LCD Interface
LVDS LCD Signals
Pixel clock to support dual channel parallel and LVDS
implementations
Reference Schematic
LM4
ACM2012H-900-2P
2
3
1
4
LM2
ACM2012H-900-2P
2
3
1
4
LM3
ACM2012H-900-2P
2
3
1
4
BKLT_VCC
LM1
ACM2012H-900-2P
2
3
1
4
LVDS0_TX0_P13
LVDS_TX1-
LVDS_TX1+
LCD_DUAL_PCK13
LVDS_TX2-
LVDS_TX2+
LVDS_TX3-
LVDS_TX3+
LM5
ACM2012H-900-2P
2
3
1
4
LVDS0_TX0_N13
LCD_VDD
BTL_PWM
CN9
HRS_DF13-20DP-1.25V(95)
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
LVDS_CLK-
LVDS_CLK+
LVDS0_TX1_N13
LVDS0_TX1_P13
LVDS_TX0-LVDS_TX0+
CN3
E-CALL_0195-01-200-020
1
1
2
2
LVDS0_TX3_P13
LVDS0_TX2_N13
LVDS0_TX2_P13
LVDS0_TX3_N13
LVDS_TX0+
LVDS_TX0-
LVDS0_CLK_P13
LVDS0_CLK_N13
LVDS_TX1+
LVDS_TX3-LVDS_TX3+
LVDS_TX2-LVDS_TX2+
LVDS_TX1-
LVDS_CLK-LVDS_CLK+
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